RISC-V /Debug /Debug Module Control (dmcontrol)

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Interpret as Debug Module Control (dmcontrol)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (inactive)dmactive 0 (ndmreset)ndmreset 0 (clrresethaltreq)clrresethaltreq 0 (setresethaltreq)setresethaltreq 0 (clrkeepalive)clrkeepalive 0 (setkeepalive)setkeepalive 0hartselhi0hartsello0 (single)hasel 0 (nop)ackunavail 0 (nop)ackhavereset 0 (hartreset)hartreset 0 (resumereq)resumereq 0 (haltreq)haltreq

dmactive=inactive, ackunavail=nop, ackhavereset=nop, hasel=single

Description

This register controls the overall Debug Module as well as the currently selected harts, as defined in {dmcontrol-hasel}.

(((hartsel))) Throughout this document we refer to {hartsel}, which is {dmcontrol-hartselhi} combined with {dmcontrol-hartsello}. While the spec allows for 20 {hartsel} bits, an implementation may choose to implement fewer than that. The actual width of {hartsel} is called HARTSELLEN. It must be at least 0 and at most 20. A debugger should discover HARTSELLEN by writing all ones to {hartsel} (assuming the maximum size) and reading back the value to see which bits were actually set. Debuggers must not change {hartsel} while an abstract command is executing. Hardware should enforce this by ignoring changes to {hartsel} while {abstractcs-busy} is set.

đź“Ś NOTE

There are separate {dmcontrol-setresethaltreq} and {dmcontrol-clrresethaltreq} bits so that it is possible to write {dm-dmcontrol} without changing the halt-on-reset request bit for each selected hart, when not all selected harts have the same configuration.

On any given write, a debugger may only write 1 to at most one of the following bits: {dmcontrol-resumereq}, {dmcontrol-hartreset}, {dmcontrol-ackhavereset}, {dmcontrol-setresethaltreq}, and {dmcontrol-clrresethaltreq}. The others must be written 0.

(((resethaltreq))) {resethaltreq} is an optional internal bit of per-hart state that cannot be read, but can be written with {dmcontrol-setresethaltreq} and {dmcontrol-clrresethaltreq}.

(((keepalive))) {keepalive} is an optional internal bit of per-hart state. When it is set, it suggests that the hardware should attempt to keep the hart available for the debugger, e.g. by keeping it from entering a low-power state once powered on. Even if the bit is implemented, hardware might not be able to keep a hart available. The bit is written through {dmcontrol-setkeepalive} and {dmcontrol-clrkeepalive}.

For forward compatibility, {dmstatus-version} will always be readable when bit 1 ({dmcontrol-ndmreset}) is 0 and bit 0 ({dmcontrol-dmactive}) is 1.

Fields

dmactive

This bit serves as a reset signal for the Debug Module itself. After changing the value of this bit, the debugger must poll {dm-dmcontrol} until {dmcontrol-dmactive} has taken the requested value before performing any action that assumes the requested {dmcontrol-dmactive} state change has completed. Hardware may take an arbitrarily long time to complete activation or deactivation and will indicate completion by setting {dmcontrol-dmactive} to the requested value. During this time, the DM may ignore any register writes.

0 (inactive): The module’s state, including authentication mechanism, takes its reset values (the {dmcontrol-dmactive} bit is the only bit which can be written to something other than its reset value). Any accesses to the module may fail. Specifically, {dmstatus-version} might not return correct data.

When this value is written, the DM may ignore any other bits written to {dmcontrol} in the same write.

1 (active): The module functions normally.

ndmreset

This bit controls the reset signal from the DM to the rest of the hardware platform. The signal should reset every part of the hardware platform, including every hart, except for the DM and any logic required to access the DM. To perform a hardware platform reset the debugger writes 1, and then writes 0 to deassert the reset.

clrresethaltreq

This optional field clears the halt-on-reset request bit for all currently selected harts.

Writes apply to the new value of {hartsel} and {dmcontrol-hasel}.

Writes to this bit should be ignored while an abstract command is executing.

setresethaltreq

This optional field writes the halt-on-reset request bit for all currently selected harts, unless {dmcontrol-clrresethaltreq} is simultaneously set to 1. When set to 1, each selected hart will halt upon the next deassertion of its reset. The halt-on-reset request bit is not automatically cleared. The debugger must write to {dmcontrol-clrresethaltreq} to clear it.

Writes apply to the new value of {hartsel} and {dmcontrol-hasel}.

If {dmstatus-hasresethaltreq} is 0, this field is not implemented.

Writes to this bit should be ignored while an abstract command is executing.

clrkeepalive

This optional field clears {keepalive} for all currently selected harts.

Writes apply to the new value of {hartsel} and {dmcontrol-hasel}.

setkeepalive

This optional field sets {keepalive} for all currently selected harts, unless {dmcontrol-clrkeepalive} is simultaneously set to 1.

Writes apply to the new value of {hartsel} and {dmcontrol-hasel}.

hartselhi

The high 10 bits of {hartsel}: the DM-specific index of the hart to select. This hart is always part of the currently selected harts.

hartsello

The low 10 bits of {hartsel}: the DM-specific index of the hart to select. This hart is always part of the currently selected harts.

hasel

Selects the definition of currently selected harts.

0 (single): There is a single currently selected hart, that is selected by {hartsel}.

1 (multiple): There may be multiple currently selected harts – the hart selected by {hartsel}, plus those selected by the hart array mask register.

ackunavail

0 (nop): No effect.

1 (ack): Clears unavail for any selected harts that are currently available.

ackhavereset

0 (nop): No effect.

1 (ack): Clears havereset for any selected harts.

hartreset

This optional field writes the reset bit for all the currently selected harts. To perform a reset the debugger writes 1, and then writes 0 to deassert the reset signal.

While this bit is 1, the debugger must not change which harts are selected.

If this feature is not implemented, the bit always stays 0, so after writing 1 the debugger can read the register back to see if the feature is supported.

Writes apply to the new value of {hartsel} and {dmcontrol-hasel}.

resumereq

Writing 1 causes the currently selected harts to resume once, if they are halted when the write occurs. It also clears the resume ack bit for those harts.

{dmcontrol-resumereq} is ignored if {dmcontrol-haltreq} is set.

Writes apply to the new value of {hartsel} and {dmcontrol-hasel}.

Writes to this bit should be ignored while an abstract command is executing.

haltreq

Writing 0 clears the halt request bit for all currently selected harts. This may cancel outstanding halt requests for those harts.

Writing 1 sets the halt request bit for all currently selected harts. Running harts will halt whenever their halt request bit is set.

Writes apply to the new value of {hartsel} and {dmcontrol-hasel}.

Writes to this bit should be ignored while an abstract command is executing.

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